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1 p/n: pm0515 features ? 5.0v 10% for read, erase and write operation ? 131072x8 only organization ? fast access time: 55/70/90/120ns ? low power consumption - 30ma maximum active current(5mhz) -1u a typical standby current ? command register architecture - byte programming (7us typical) - sector erase (8k-byte x 1, 4k-byte x 2, 8k byte x 2, 32k-byte x 1, and 64k-byte x 1) ? auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability. - automatically programs and verifies data at specified address ? erase suspend/erase resume C suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. ? status reply - data polling & toggle bit for detection of program and erase cycle completion. ? chip protect/unprotect for 5v only system or 5v/12v system ? 100,000 minimum erase/program cycles ? latch-up protected to 100ma from -1 to vcc+1v ? boot code sector architecture - t = top boot sector - b = bottom boot sector ? low vcc write inhibit is equal to or less than 3.2v ? package type: - 32-pin plcc - 32-pin tsop - 32-pin pdip ? boot code sector architecture - t=top boot sector - b=bottom boot sector ? 20 years data retention general description the mx29f001t/b is a 1-mega bit flash memory organized as 128k bytes of 8 bits only mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the mx29f001t/b is packaged in 32-pin plcc, tsop, pdip. it is designed to be repro- grammed and erased in-system or in-standard eprom programmers. the standard mx29f001t/b offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx29f001t/b has separate chip enable (ce) and output enable (oe) controls. mxic's flash memories augment eprom function- ality with in-circuit electrical erasure and programming. the mx29f001t/b uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combi- nation of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29f001t/b uses a 5.0v 10% vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. mx29f001t/b 1m-bit [128k x 8] cmos flash memory rev. 2.5, nov. 20, 2002
2 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b pin configurations 32 tsop (type 1) pin description: (normal type) sector structure mx29f001t sector architecture mx29f001b sector architecture symbol pin name a0~a16 address input q0~q7 data input/output ce chip enable input we write enable input oe output enable input vcc power supply pin (+5v) gnd ground pin mx29f001t/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we nc a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 nc vcc we nc mx29f001t/b a11 a9 a8 a13 a14 nc we vcc nc a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29f001t/b 8 k-byte 00000h 64 k-byte 32 k-byte 8 k-byte 8 k-byte 4 k-byte 4 k-byte 1ffffh 0ffffh 05fffh 02fffh 01fffh 03fffh a16~a0 07fffh 64 k-byte 00000h 8 k-byte 4 k-byte 4 k-byte 8 k-byte 8 k-byte 32 k-byte 1ffffh 1dfffh 1cfffh 19fffh 17fffh 0ffffh 1bfffh a16~a0 32 plcc 32 pdip
3 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx29f001t/b flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a16 ce oe we
4 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b automatic programming the mx29f001t/b is byte programmable using the au- tomatic programming algorithm. the automatic program- ming algorithm does not require the system to time out or verify the data programmed. the typical chip pro- gramming time of the mx29f001t/b at room tempera- ture is less than 3.5 seconds. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 3 second. the automatic erase algorithm au- tomatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are internally controlled within the device. automatic sector erase the mx29f001t/b is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm automatically pro- grams the specified sector(s) prior to electrical erase. the timing and verification of electrical erase are inter- nally con trolled by the device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write program set-up commands (include 2 unlock write cycle and a0h) and a program command (program data and address). the device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. a status bit similar to data polling and a status bit tog- gling between consecutive read cycles, provides feed- back to the user as to the status of the programming operation. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches addresses and data needed for the pro- gramming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the mx29f001t/b elec- trically erases all bits simultaneously using fowler- nordheim tunneling. the bytes are programmed by us- ing the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
5 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 rd rd read silicon id 4 555h aah 2aah 55h 555h 90h adi ddi chip protect verify 4 555h aah 2aah 55h 555h 90h (sa) 00h x02h 01h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h unlock for chip 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 20h protect/unprotect table 1. software command definitions note: 1. adi = address of device identifier;a1=0, a0 =0 for manufacture code, a1=0, a0 =1 for device code.(refer to table 3) ddi = data of device identifier : c2h for manufacture code, 18h/19h for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address to the sector to be erased. 3. the system should generate the following address patterns: 555h or 2aah to address a0~a10. address bit a11~a16=x=don't care for all address commands except for program address (pa) and sector address (sa). write sequence may be initiated with a11~a16 in either state. 4. for chip protect verify operation : if read out data is 01h, it means the chip has been protected. if read out data is 00h, it means the chip is still not being protected. command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 1 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device(when applicable).
6 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b pins ce oe we a0 a1 a6 a9 q0 ~ q7 mode read silicon id l l h l l x v id (2) c2h manufacturer code(1) read silicon id l l h h l x v id (2) 18h/19h device code(1) read l l h a0 a1 a6 a9 d out standby h x x x x x x high z output disable l h h x x x x high z write l h l a0 a1 a6 a9 d in (3) chip protect with 12v l v id (2) l x x l v id (2) x system(6) chip unprotect with 12v l v id (2) l x x h v id (2) x system(6) verify chip protect l l h x h x v id (2) code(5) with 12v system chip protect without 12v l h l x x l h x system (6) chip unprotect without 12v l h l x x h h x system (6) verify chip protect/unprotect l l h x h x h code(5) without 12v system (7) reset x x x x x x x high z table 2. mx29f001t/b bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 1 for valid data-in during a write operation. 4. x can be vil or vih. 5. code=00h means unprotected. code=01h means protected. 6. refer to chip protect/unprotect algorithm and waveform. must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12v system" command. 7. the "verify chip protect/unprotect without 12v system" is only following "chip protect/unprotect without 12v system" command.
7 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b read/reset command the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data. the de- vice remains enabled for reads until the command regis- ter contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid com- mand must then be written to place the device in the desired state. silicon-id-read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. the mx29f001t/b contains a silicon-id-read operation to supplement traditional prom programming method- ology. the operation is initiated by writing the read sili- con id command sequence into the command register. following the command write, a read cycle with a1=vil,a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of 18h for mx29f001t,19h for mx29f001b. pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code (hex) code manufacture code vil vil 1 1 0 0 0 0 1 0 c2h device code vih vil 0 0 0 1 1 0 0 0 18h for mx29f001t device code vih vil 0 0 0 1 1 0 0 1 19h for mx29f001b chip protection verification x vih 0 0 0 0 0 0 0 1 01h (protected) x vih 0 0 0 0 0 0 0 0 00h (unprotected) table 3. expanded silicon id code set-up automatic chip erase com- mands chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verification begin. the erase and verification operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system does not require to pro- vide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). if the erase operation was unsuccessful, the data on q5 is "1"(see table 4), indicating an erase operation exceed internal timing limit. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode.
8 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b sector erase commands the automatic sector erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic set-up sector erase command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. the system does not require to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verifi- cation begin. the erase and verification operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system does not require to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up com- mand 80h. two more "unlock" write cycles are then fol- lowed by the sector erase command 30h. the sector address is latched on the falling edge of we, while the command(data) is latched on the rising edge of we. sec- tor addresses selected are loaded into internal register on the sixth falling edge of we. each successive sector load cycle started by the falling edge of we must begin within 30us from the rising edge of the preceding we. otherwise, the loading period ends and internal auto sec- tor erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase (30h) or erase suspend (b0h) during the time-out period resets the device to read mode. erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. writing the erase suspend com- mand during the sector erase time-out immediately ter- minates the time-out immediately terminates the time- out period and suspends the erase operation. after this command has been executed, the command register will initiate erase suspend mode. the state machine will re- turn to read mode automatically after suspend is ready. at this time, state machine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors.
9 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b status q7 q6 q5 q3 byte program in auto program algorithm q7 toggle 0 n/a in progress auto erase algorithm 0 toggle 0 1 erase suspended mode erase suspend read data data data data erase suspend program q7 toggle 0 n/a (non-erase suspended sector) (note1) byte program in auto program algorithm q7 toggle 1 n/a exceeded erase in auto erase algorithm 0 toggle 1 1 time limits erase suspended mode erase suspend program q7 toggle 1 n/a (non-erase suspended sector) table 4. write operation status note: 1. performing successive read operations from any address will cause q6 to toggle.
10 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing. set-up automatic program commands to initiate automatic program mode, a three-cycle com- mand sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic pro- gram command a0h. once the automatic program command is initiated, the next we pulse causes a transition to an active program- ming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we pulse. the rising edge of we also begins the programming operation. the system does not require to provide further controls or timings. the device will auto- matically provide an adequate internally generated pro- gram pulse and verify margin. if the program operation was unsuccessful, the data on q5 is "1"(see table 4), indicating the program operation exceed internal timing limit. the automatic programming operation is completed when the data read on q6 stops toggling for two consecutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode (no program verify command is required). write operation status toggle bit-q6 the mx29f001t/b features a "toggle bit" as a method to indicate to the host system that the auto program/ erase algorithms are either in progress or complete. while the automatic program or erase algorithm is in progress, successive attempts to read data from the device will result in q6 toggling between one and zero. once the automatic program or erase algorithm is com- pleted, q6 will stop toggling and valid data will be read. the toggle bit is valid after the rising edge of the sixth we pulse of the six write pulse sequences for chip/sec- tor erase. the toggle bit feature is active during automatic pro- gram/erase algorithms or sector erase time-out. (see section q3 sector erase timer) data polling-q7 the mx29f001t/b also features data polling as a method to indicate to the host system that the auto- matic program or erase algorithms are either in progress or completed. while the automatic programming algorithm is in opera- tion, an attempt to read the device will produce the comple- ment data of the data last written to q7. upon comple- tion of the automatic program algorithm an attempt to read the device will produce the true data last written to q7. the data polling feature is valid after the rising edge of the fourth we pulse of the four write pulse sequences for automatic program. while the automatic erase algorithm is in operation, q7 will read "0" until the erase operation is competed. upon completion of the erase operation, the data on q7 will read "1". the data polling feature is valid after the rising edge of the sixth we pulse of six write pulse sequences for automatic chip/sector erase. the data polling feature is active during automatic pro- gram/erase algorithm or sector erase time-out.(see sec- tion q3 sector erase timer)
11 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b q5 exceeded timing limits q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data polling and toggle bit are the only operating functions of the device under this condi- tion. if this time-out condition occurs during sector erase op- eration, it is specifies that a particular sector is bad and it may not be reused. however, other sectors are still functional and may be used for the program or erase operation. the device must be reset to use other sec- tors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other ac- tive sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector may not be re- used, (other sectors are still functional and can be re- used). the time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the au- tomatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. q3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. q3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase com- mand sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if q3 is low ("0"), the device will accept addi- tional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. data protection the mx29f001t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory con- tents only occurs after successful completion of spe- cific command sequences. the device also incorporates several features to prevent inadvertent write cycles re- sulting from vcc power-up and power-down transition or system noise.
12 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd. (using a 10uf bulk capacitor connected for high current condition is available if nec- essary.) chip protection with 12v system the mx29f001t/b features hardware chip protection. which will disable both program and erase operations. to activate this mode, the programming equipment must force vid on address pin a9 and control pin oe, (sug- gest vid=12v) a6=vil and ce=vil.(see table 2) pro- gramming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. please refer to chip protect algorithm and waveform. to verify programming of the protection circuitry, the pro- gramming equipment must force vid on address pin a9 ( with ce and oe at vil and we at vih. when a1=1, it will produce a logical "1" code at device output q0 for the protected status. otherwise the device will produce 00h for the unprotected status. in this mode, the ad- dress, except for a1, are don't care. address locations with a1 = vil are reserved to read manufacturer and device codes.(read silicon id) it is also possible to determine if the chip is protected in the system by writing a read silicon id command. per- forming a read operation with a1=vih, it will produce a logical "1" at q0 for the protected status. chip unprotect with 12v system the mx29f001t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect completion to incorporate any changes in the code. to activate this mode, the programming equipment must force vid on control pin oe and address pin a9. the ce pins must be set at vil. pins a6 must be set to vih.(see table 2) refer to chip unprotect algorithm and wave- form for the chip unprotect algorithm. the unprotection mechanism begins on the falling edge of the we pulse and is terminated with the rising edge of the same. it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs (q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. chip protection without 12v system the mx29f001t/b also feature a hardware chip protec- tion method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to protect all sectors. the details are shown in chip pro- tect algorithm and waveform. chip unprotect without 12v system the mx29f001t/b also feature a hardware chip unprotection method in a system without 12v power sup- ply. the programming equipment do not need to supply 12 volts to unprotect all sectors. the details are shown in chip unprotect algorithm and waveform. power-up sequence the mx29f001t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command se- quences.
13 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 & oe -0.5v to 13.5v notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. symbol parameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v read operation dc characteristics vcc = 5v 10% (vcc = 5v 5% for 29f001t/b-55) symbol parameter min. typ max. unit conditions ili input leakage current 1 ua vin = gnd to vcc ilo output leakage current 10 ua vout = gnd to vcc isb1 standby vcc current 1 ma ce = vih isb2 1 5 ua ce = vcc + 0.3v icc1 operating vcc current 30 ma iout = 0ma, f=5mhz icc2 50 ma iout = 0ma, f=10mhz vil input low voltage -0.3(note 1) 0.8 v vih input high voltage 2.0 vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma voh1 output high voltage(ttl) 2.4 v ioh = -2ma voh2 output high voltage(cmos) vcc-0.4 v ioh = -100ua vcc=vcc min notes: 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed. capacitance ta = 25 o c, f = 1.0 mhz
14 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b ac characteristics vcc = 5v 10% (5v 5% for mx29f001t/b-55) note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: ? input pulse levels: 0.45v/2.4v for 70ns max. ; 0v/3.0v for 55ns ? input rise and fall times: <10ns for 70ns max; <5ns for 55ns ? output load: 1 ttl gate + 100pf (including scope and jig) for 70ns max. ; 1 ttl gate + 30pf (including scope and jig) for 55ns max. ? reference levels for measuring timing : 0.8v & 2.0v for 70ns max.; 1.5v for 55ns 29f001t/b-55 29f001t/b-70 symbol parameter min. max. min. max. unit conditions tacc address to output delay 55 70 ns ce=oe=vil tce ce to output delay 55 70 ns oe=vil toe oe to output delay 30 40 ns ce=vil tdf oe high to output float (note1) 0 20 0 20 ns ce=vil toh address to output hold 0 0 ns ce=oe=vil 29f001t/b-90 29f001t/b-12 symbol parameter min. max. min. max. unit conditions tacc address to output delay 90 120 ns ce=oe=vil tce ce to output delay 90 120 ns oe=vil toe oe to output delay 40 50 ns ce=vil tdf oe high to output float (note1) 0 30 0 30 ns ce=vil toh address to output hold 0 0 ns ce=oe=vil
15 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b symbol parameter min. typ max. unit conditions icc1 (read) operating vcc current 30 ma iout=0ma, f=5mhz icc2 50 ma iout=0ma, f=10mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icces vcc erase suspend current 2 ma ce=vih, erase suspended command programming/data programming/erase operation notes: 1. vil min. = -0.6v for pulse width < 20ns. 2. if vih is over the specified maximum value, programming operation cannot be guaranteed. 3. icces is specified with the device de-selected. if the device is read during erase suspend mode, current draw is the sum of icces and icc1 or icc2. 4. all current are in rms unless otherwise noted. read timing waveforms a0~16 ce oe tacc we vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tdf tce data q0~7 toh add valid dc characteristics vcc = 5v 10% (vcc = 5v 5% for 29f001t/b-55)
16 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b 29f001t/b-70 29f001t/b-90 29f001t/b-12 symbol parameter min. max. min. max. min. max. unit toes oe setup time 0 0 0 ns tcwc command programming cycle 70 90 120 ns tcep we programming pulse width 45 45 50 ns tceph1 we programming pulse width high 20 20 20 ns tceph2 we programming pulse width high 20 20 20 ns tas address setup time 0 0 0 ns tah address hold time 45 45 50 ns tds data setup time 30 45 50 ns tdh data hold time 0 0 0 ns tcesc ce setup time before command write 0 0 0 ns tdf output disable time (note 1) 30 40 40 ns taetc total erase time in auto chip erase 3(typ.) 24 3(typ.) 24 3(typ.) 24 s taetb total erase time in auto sector erase 1(typ.) 8 1(typ.) 8 1(typ.) 8 s tavt total programming time in auto verify 7 210 7 210 7 210 us tbal sector address load time 100 100 100 us tch ce hold time 0 0 0 ns tcs ce setup to we going low 0 0 0 ns tvlht voltage transition time 4 4 4 us toesp oe setup time to we active 4 4 4 us twpp write pulse width for chip protect 10 10 10 us twpp2 write pulse width for chip unprotect 12 12 12 ms notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven. ac characteristics vcc = 5v 10% (vcc = 5v 5% for 29f001t/b-55)
17 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b ac characteristics vcc = 5v 5% for mx29f001t/b-55 29f001t/b-55 symbol parameter min. max. unit toes oe setup time 0 ns tcwc command programming cycle 70 ns tcep we programming pulse width 45 ns tceph1 we programming pulse width high 20 ns tceph2 we programming pulse width high 20 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 20 ns tdh data hold time 0 ns tcesc ce setup time before command write 0 ns tdf output disable time (note 1) 20 ns taetc total erase time in auto chip erase 3(typ.) 24 s taetb total erase time in auto sector erase 1(typ.) 8 s tavt total programming time in auto verify 7 210 us tbal sector address load time 100 us tch ce hold time 0 ns tcs ce setup to we going low 0 ns tvlht voltage transition time 4 us toesp oe setup time to we active 4 us twpp write pulse width for chip protect 10 us twpp2 write pulse width for chip unprotect 12 ms notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven.
18 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b switching test circuits switching test waveforms(i) for 29f001t/b-70, 29f001t/b-90, 29f001t/b-12 switching test waveforms(ii) for 29f001t/b-55 3.0 v 0 v 1.5v test points input 1.5v output ac testing: inputs are driven at 3.0v for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 5ns. 2.0v 2.4 v 0.45 v 0.8v test points input 2.0v 0.8v output ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are < 10ns. device under test diodes=in3064 or equivalent cl 1.2k ohm 1.6k ohm +5v cl=100pf including jig capacitance for 29f001t/b-70, 29f001t/b-90, 29f001t/b-12 30pf including jig capacitance for 29f001t/b-55
19 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b command write timing waveform add a0~16 ce oe we din tds tah data q0-7 tdh tcs tch tcwc tceph1 tcep toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid
20 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b automatic programming timing waveform one byte data is programmed. verification in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. programming completion can be verified by data polling and toggle bit automatic programming timing waveform checking after automatic verify starts. device outputs data during programming and data after programming on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) tcwc tas tcep tds tdh tdf vcc 5v ce oe q0~q2 ,q4(note 1) we a11~a16 tceph1 tah add valid tcesc q7 command in add valid a0~a10 command in command in data in data command in command in command in data in data data tavt toe data polling 2aah 555h 555h command #aah command #55h command #a0h (q0~q7) notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit
21 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes no toggle bit checking q6 not toggled verify byte ok yes q5 = 1 reset auto program completed auto program exceed timing limit no invalid command yes no .
22 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b toggle bit algorithm notes: 1.read toggle bit q6 twice to determine whether or not it is toggle. see text. 2.recheck toggle bit q6 because it may stop toggling as q5 changes to "1". see text. start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no no (note 1) read q7~q0 twice (note 1,2) toggle bit q6= toggle? program/erase operation not complete, write reset command yes program/erase operation complete
23 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b matic erase starts. device outputs 0 during erasure and 1 after erasure 0n q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) all data in chip are erased. external erase verification is not required because data is erased automatically by internal control circuit. erasure completion can be veri- fied by data polling and toggle bit checking after auto automatic chip erase timing waveform tcwc tas tcep tds tdh vcc 5v ce oe q0,q1, q4(note 1) we a11~a16 tceph1 tah q7 command in a0~a10 command in command in command in command in command in taetc data polling 2aah 555h 555h command #aah command #55h command #80h (q0~q7) notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit 555h 2aah 555h command in command in command #aah command in command in command #55h command in command in command #10h automatic chip erase timing waveform
24 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 10h address 555h write data 55h address 2aah reset auto chip erase exceed timing limit data polling q7 = 1 yes yes q5 = 1 auto chip erase completed no . no invalid command
25 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b automatic sector erase timing waveform sector data indicated by a13 to a16 are erased. external erase verify is not required because data are erased automatically by internal control circuit. erasure comple- tion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic sector erase timing waveform tah sector address0 555h 2aah 2aah 555h 555h sector address1 sector addressn vcc 5v ce oe q0,q1, q4(note 1) we a13~a16 q7 a0~a10 command in command in command in command in command in command in command in command in command in command in command in command in command in command in command #30h command #30h command #30h command #55h command #aah command #80h command #55h command #aah (q0~q7) command in command in tdh tds tcep tcwc taetb tbal data polling tceph1 tas notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit
26 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes yes no no . toggle bit checking q6 not toggled write data 30h sector address write data 55h address 2aah reset auto sector erase exceed timing data polling q7 = 1 q5 = 1 auto sector erase completed load other sector addrss if necessary (load other sector address) yes no last sector to erase time-out bit checking q3=1 ? toggle bit checking q6 toggled ? invalid command no yes yes no
27 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no . yes yes no
28 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b timing waveform for chip protection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h f0h
29 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b timing waveform for chip unprotection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 f0h
30 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b chip protection algorithm for system with 12v start plscnt=1 chip protection complete data=01h? oe=vid,a9=vid,ce=vil a6=vil activate we pulse time out 10us set we=vih, ce=oe=vil a9 should remain vid read from sector addr=sa, a1=1 remove vid from a9 write reset command device failed plscnt=32? ye s no device failed no
31 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b chip unprotection algorithm for system with 12v start plscnt=1 chip unprotect complete data=00h? set oe=a9=vid ce=vil,a6=1 activate we pulse time out 12ms set oe=ce=vil a9=vid,a1=1 remove vid from a9 write reset command device failed plscnt=1000? increment plscnt no read data from device ye s ye s no
32 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b timing waveform for chip protection for system without 12v toe data oe we ce a1 a6 * see the following note! verify 01h 5v note: 1. must issue "unlock for sector protect/unprotect" command before chip protection for a system without 12v provided. 2. except f0h toggle bit polling don't care (note 2) tcep f0h
33 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b timing waveform for chip unprotection for system without 12v toe data we ce a1 verify 00h a6 note: 1. must issue "unlock for sector protect/unprotect" command before chip unprotection for a system without 12v provided. 2. except f0h oe tcep 5v toggle bit polling don't care (note 2) * see the following note! f0h
34 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b chip protection algorithm for system without 12v start plscnt=1 chip protection complete data=01h? oe=vih,a9=vih ce=vil,a6=vil activate we pulse to start data don't care set ce=oe=vil a9=vih raed from sector addr=sa, a1=1 write reset command device failed plscnt=32? ye s no increment plscnt no write "unlock for chip protect/unprotect" command(table1) toggle bit checking dq6 not toggled no . ye s ye s
35 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b chip unprotection algorithm for system without 12v start plscnt=1 chip unprotect complete data=00h? set oe=a9=vih ce=vil,a6=1 activate we pulse to start data don't care set oe=ce=vil a9=vih,a1=1 write reset command device failed plscnt=1000? increment plscnt no read data from device ye s ye s no write "unlock for chip protect/unprotect" command (table 1) toggle bit checking dq6 not toggled ye s no
36 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b id code read timing waveform tacc tce tacc toe toh toh tdf data out c2h 18h/19h vid vih vil add a9 add a2-a8 a10-a16 ce oe we a1 data out data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil
37 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. limits parameter min. typ.(2) max.(3) units sector erase time 1 8 s chip erase time 3 24 s byte programming time 7 210 us chip programming time 3.5 10.5 sec erase/program cycles 100,000 cycles latch-up characteristics erase and programming performance (1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c, 5v. 3.maximum values measured at 25 c, 4.5v. parameter min. unit data retention time 20 years data retention
38 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b ordering information plastic package (top boot sector as an sample for bottom boot sector ones,mx29f001txx will change to mx29f001bxx) part no. access time operating current standby current package (ns) max.(ma) max.(ua) mx29f001tqc-55 55 30 5 32 pin plcc mx29f001tqc-70 70 30 5 32 pin plcc mx29f001tqc-90 90 30 5 32 pin plcc mx29f001tqc-12 120 30 5 32 pin plcc mx29f001ttc-55 55 30 5 32 pin tsop (normal type) mx29f001ttc-70 70 30 5 32 pin tsop (normal type) mx29f001ttc-90 90 30 5 32 pin tsop (normal type) mx29f001ttc-12 120 30 5 32 pin tsop (normal type) mx29f001tpc-55 55 30 5 32 pin pdip mx29f001tpc-70 70 30 5 32 pin pdip mx29f001tpc-90 90 30 5 32 pin pdip mx29f001tpc-12 120 30 5 32 pin pdip
39 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b package information
40 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b
41 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b
42 rev. 2.5,nov. 20, 2002 p/n: pm0515 mx29f001t/b revision description page date 2.0 1. to remove "advanced information" data sheet marking and p1 dec/21/1999 contain information on products in full production 2.the modification summary from revision 0.0 to revision 1.0: 2-1.program/erase cycle times:10k cycles-->100k cycles p1,38 2-2.to add data retention 20 years p1,38 2-3.to remove a9 from the timing waveform of protection/ p32,33 unprotection without 12v 2-4.multi-sector erase time out:80ms-->30us p8 2-5.tbal:80us-->100us p16,17 2.1 to modify "package information" p39~41 jun/14/2001 2.2 to corrected typing error all jul/01/2002 2.3 1. add industrial grade spec p13,38 jul/09/2002 2. modify maximum value measurement temperature from 25 c to 85 c p37 2.4 1. remove industrial grade spec p13,37,38 aug/12/2002 2.5 1. to modify package information p39~41 nov/20/2002 revision history
mx29f001t/b m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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